An amplifier with a cascode transistor is known from an article titled “A 2.4-GHz 0.18- m CMOS Self-Biased Cascode Power Amplifier”, by Tirdad Sowlati, and Domine M. W. Leenaerts and published in the IEEE Journal of Solid-State Circuits, vol. 38, no. 8, Aug. 2003. This amplifier has a resonant load circuit that has the effect that voltage across at the drain of the cascode transistor can swing to several times the power supply voltage Vdd. This gives rise to a risk of cascode transistor breakdown. The article proposes to make the gate voltage of the cascode transistor swing with an attenuated version of the output swing.
FIG. 1 shows one embodiment of an amplifier. The circuit comprises and amplifier transistor 10, a cascode transistor 12 and a resonant load circuit 14. The drain of the cascode transistor 12 is coupled to its gate by a resistor 16 and the gate is coupled to ground via a capacitor 18. Thus an RC circuit is used to generate an attenuated swing at the gate of the cascode transistor. This solves the breakdown problem by reducing the voltage differences between the terminals of the cascode transistor.
U.S. Pat. No. 4,317,055 describes a high voltage cascode amplifier that is protected against unduly high power supply voltages of hundreds of volts by deriving the gate voltage from the power supply voltage with a voltage divider. This reduces the static voltage differences between the terminals of the cascode transistor. Thereby the power supply voltage at which breakdown occurs is increased. Moreover this patent proposes to use an additional voltage source to raise the gate voltage above the voltage obtained from the voltage divider by at least a transistor threshold voltage. This is used to avoid that the cascode transistors is biased below its threshold, which would dramatically increase the “on” resistance of the channel of the cascode transistors.
Neither document addresses the optimization of the efficiency of the amplifier.